1. Field of the Invention
The present invention relates to a run length code decoder for decoding a run length coded signal used in a facsimile machine.
2. Description of the Prior Art
In the past, a modified Huffman code (hereinafter referred to as an MH code) shown in FIGS. 1(A) and 1(B) has been used as a redundancy suppressing system in a facsimile machine. As shown in FIGS. 1(A) and 1(B), in the MH code, run lengths 0-1728 are divided into groups each comprising 64 run lengths and each run length is represented by a combination of a make-up code which represents a group (and which is a multiple of 64 such as 64, 128, 192, . . . 1728 as shown in FIG. 1(B)) and a terminating code which represents a specific run length in the group (0, 1, 2, 3, . . . 63 as shown in FIG. 1(A)). For example, a white run length "65" is represented by a combination of a code word "11011" which represents 64 and a code word "000111" which represents 1.
In decoding such an MH code, all MH codes are stored in a memory such as a ROM (read-only memory) for a data table in a form of a so-called code tree by using a micro-processor, and the memory is accessed at each node of the tree each time when one bit of a data to be decoded is inputted to sequentially select branches of the tree so that a memory address of a terminal node at which a decoded result is stored is finally reached. In this decoding method, since the memory must be accessed for each input of one bit of the data, processing steps are necessarily large in number and a processing time is long. Thus, in order to attain a practically acceptable processing speed, an expensive fast micro-processor or a fast wired logic circuit is required.